Traditional binary logic circuits communicate information using two states that include a low voltage state or logic zero and a high voltage state or logic one. Using predetermined voltage levels for logic zero and logic one, these circuits communicate information at a given clock speed, where each cycle of the clock may represent a logic one or a logic zero. Several binary logic standards such as Gunning Transceiver Logic (GTL) and Stub Series Terminated Logic (SSTL) define the different voltage levels and timing requirements to allow receivers to resolve the logic zero and logic one signals.
Given a fixed number of data lines and a predetermined clock frequency, the amount of information communicated by existing binary logic standards is limited. The allowed bandwidth on existing data lines using binary logic may be insufficient to satisfy increasing capacity demands in a variety of communication systems. Moreover, current approaches may not allow both an increase in the amount of data for communication on a data line as well as backwards compatibility to existing binary logic standards.